1. Field of the Invention
This invention generally relates to digital-to-analogue converters (DACs). More particularly it relates to differential, current-steering DACs with reduced small signal differential non-linearity.
2. Related Art
Background references relating to current-steering DACs can be found in: US2003227402; US6853323; WO03021790; US6507304; US2003/001765; US2006/0012501; U.S. Pat. No. 6,967,609; WPO 2005/117402; US2005/0225465; U.S. Pat. No. 6,927,714; U.S. Pat. No. 6,833,801; US2004/0119621; U.S. Pat. No. 6,720,898; U.S. Pat. No. 6,703,956; U.S. Pat. No. 6,741,195; US2003/112164; US2003/001656; WO0215421; US2002/030619; U.S. Pat. No. 6,339,391; U.S. Pat. No. 5,909,187; U.S. Pat. No. 5,748,127; U.S. Pat. No. 5,463,394; EP0511858; WO01/67614; EP 0 251 758A; JP07-336227; and JP60-245315, which are all incorporated by reference herein in their entirety.
FIG. 1 shows a circuit diagram of a binary weighted current-steering DAC 10. This is configured to convert an m-bit digital input word into a differential analogue output signal (VO−, VO+) on differential output line 12a, 12b. The DAC 10 includes a plurality of binary weighted current sinks 14a-d, each of value 2i I0 where i runs from 0 to m. Each current sink has a respective switch 16 which switches the current between either the first or the second differential output line 12a, b responsive to the binary digital input signal, thus steering the current from each source to one or other of the two load resistors 18, thus forming a differential analogue signal at the output, in here a voltage signal. In this way each digital bit controls a current source which is weighted according to the significance of the controlling bit.
FIG. 1 shows the case of an 8 bit DAC architecture. In the diagram, the variable “x” represents an integer (binary digital value) between 0 and 255. I0 is the value of the smallest current source. As shown above, a small offset current of I0 may be included at the lower end of the DAC. This ensures zero differential output for x=128.
Table 1, below, shows how the digital value X maps to an output voltage in a differential current-steering DAC. The architecture shown in FIG. 1 can also be employed with a signed, twos complement digital data format with a simple logic change, that is inverting the MSB (most significant bit).
TABLE 1(VO+ − VO−)/xVO+VO−VO+ − VO−2I0RL255VDD − I0RLVDD − 255I0RL254I0RL127254VDD − 2I0RLVDD − 254I0RL252I0RL126253VDD − 3I0RLVDD − 253I0RL250I0RL125. . .. . .. . .. . .. . .129VDD − 127I0RLVDD − 129I0RL2I0RL1128VDD − 128I0RLVDD − 128I0RL00127VDD − 129I0RLVDD − 127I0RL−2I0RL−1. . .. . .. . .. . .. . . 2VDD − 253I0RLVDD − 2I0RL−252I0RL−126 1VDD − 254I0RLVDD − I0RL−254I0RL−127 0VDD − 255I0RLVDD−256I0RL−128
We next discuss linearity errors.
In a real implementation, the values of the current sources will be subject to fine tolerances. This produces errors in the output levels. There are two measurements commonly used to quantify the errors-integral non-linearity (INL) and differential non-linearity (DNL). These are defined in terms of the deviation of the DAC transfer function from a straight line. (The straight line is generated either by a least-squares method or by end-point fitting. The gain error is treated as a separate specification).
Definitions:LSBThe average voltage step produced by changing the digital inputvalue by 1 (i.e the slope of the transfer function). Stands for“Least Significant Bit”.DNLThe worst-case error in the size of the voltage or current stepbetween any two adjacent codes. Always normalised to 1 LSB.INLThe worst-case deviation of the transfer function from the idealstraight line. Always normalised to 1 LSB.
INL and DNL are different ways of looking at the same errors, and they contain essentially the same information. Here it is convenient to focus on DNL errors. For more information on INL and DNL, reference may be made to Dan Sheingold, Analog-Digital Conversion Handbook, 3rd Edition, Analog Devices and Prentice-Hall, 1986, ISBN-0-13-032848-0.
A plot of the DNL error at each input code follows a distinctive patter. The worst error is usually at the “major bit transition”, which occurs at the centre of the DAC range. The significance of this is discussed later.
In the 8-bit case, this is the transition from 127 to 128:
DecimalBinary1270111111112810000000
In the binary DAC of FIG. 1, all currents are redirected from one output terminal to the other at this transition. This means that all the errors added together, and the total error can be very large. Of course it is also possible that the errors will cancel each other out, since this is a statistical process. However a practical design should aim to ensure that the total error is acceptably small for a large percentage of die; 3σ limits are typically used.
We next consider RF (Radio Frequency) communications systems, and in particular OFDM (Orthogonal Frequency Division Multiplexed) communications systems. Further reference may be made to standard ECMA-368, First Edition, 2005 “High Rate Ultra Wide Band PHY and MAC standard”, which specifies the UWB (Ultra Wide Band) physical layer and medium access control layer for a high speed short range wireless network using the spectrum between 3.1 GHz and 10.6 GHz. This document is hereby incorporated by reference. In this UWB standard a multiBand OFDM (MB-OFDM) scheme is used to transmit information with frequency-domain spreading, time-domain spreading and forward error correction (FEC) coding.
Broadly speaking in an OFDM communications system data is carried on a set of substantially mutually orthogonal sub-carriers, which together comprise an OFDM symbol. Because multiple sub-carriers are employed the effective data rate on each sub-carrier is relatively low. Because the sub-carriers are orthogonal they can overlap in frequency and still be separated at the receiver—this is because, in effect, during an integration over the period of one sub-carrier, the other sub-carriers averaged zero.
To generate an OFDM symbol an inverse Fourier transform is performed on a set of input symbols, the sub-carriers are orthogonal if they are spaced apart in frequency by an interval of 1/T, where T is the OFDM symbol period. At the receiver the input symbols can be recovered by performing a Fourier transform. A range of sub-carrier modulation schemes may be employed, for example PAM (Pulse Amplitude Modulation) and PSK (Phase Shift Keying), although commonly, and in the aforementioned UWB systems, QAM (Quadrature Amplitude Modulation) is employed. To reduce the effects of multipath OFDM symbols are normally extended by a guard period at the start or end of each symbol so that no ISI (Inter Symbol Interference) or ICI (Inter-Carrier Interference) will occur between signals with a difference in propagation time less than this guard period.
FIG. 2a shows a simplified block diagram of a OFDM transmitter 50 of the general type employed in many communications systems including UWB communications systems. An initial data stream is fed to a coding and interleaving stage 54 which performs outer Reed-Solomon coding and interleaving and inner convolutional coding and interleaving. QAM modulation mapping 56 is then performed and the pilot tones and TPS (Transmission Parameter Signalling) data (which specifies parameters such as modulation type, guard interval and inner code rates) are then inserted 58. OFDM modulation 60 is then performed, typically by serial-to-parallel conversion, an Inverse Fast Fourier Transform (IFFT) and subsequent parallel-to-serial conversion. The guard period is then inserted 62 by adding a cyclic prefix to the OFDM symbol and the signal is passed to a digital-to-analogue converter 64, which provides an analogue output to an RF output stage 66.
FIG. 2b, which is taken from FIG. 4 of standard ECMA-368, shows conversion from discrete time signals to continuous time signals in more detail showing that a pair of DACS, for real and imaginary components of the signal, may be employed together with anti-aliasing filters as indicated.
We next analyze the DAC stage of an OFDM system by considering some assume characteristics of the transmitted OFDM signal.
1. The digital baseband signal contains no DC component. Its amplitude varies symmetrically about zero.
2. The peak-to-average ratio can be large—i.e. it is likely that, at any given moment in time, the signal will be close to zero.
The first assumption suggests biasing the signal at the centre of the DAC range. This is simply a matter of adding 128 to the digital input signal. However, the worst-case static error in the DAC is at the transition from 127 to 128 and this centres the signal at the worst possible place in the transfer function. Further according to assumption (2) above, the signal is likely to spend a lot of time in this region.